It is certainly possible to achieve 500 Msps with one of the low end FPGAs, but you are approaching the limits of those devices. If this is your first go around, and your running low quantity, I would buy an eval board and use that.Īnother thing is there might be better ways to make your measurement than a 500MHz ADC, something like an SDR can go well past 500Mhz and be better for your application depending on the bandwidth If you've never done high speed, I would not cut your teeth on this type of design unless you have a consultant or someone who has done it before around. Make sure you know how to impedance match the traces. Make sure you have the right equipment before attempting a very high speed design, you'll need at minimum a differential probe that runs 2x the frequency of your fastest I/O speed for troubleshooting. Note that this is an embedded application, so stringing together someĭev boards can be effective to prove out chip performance, but The most important one would be the I/O that the ADC uses, high speed ADC's use trancievers most of the time, you'll need to make sure the transciever operates faster than the rate of the ADC, for example the spartian 6 datasheet has info on how fast the LVDS transceivers can operate: What are the key datasheet parameters I should be paying attention to One thing for sure is no logic will run faster than the clock speed of the FPGA, and the logic will always run a bit slower (because of cascaded gate delays). The way to check is the datasheet of each device, which is tedious. There are many factors that determine how fast logic can run in an FPGA, most of the time you won't know until you put logic on the FPGA because the delays in the logic determine how fast the logic can operate. Looking at is fast enough to keep up with my ADC? How can I tell if one of the cheap FPGAs (example: Spartan-6) I'm I want to understand the FPGA I/O bottlenecks so I can choose a cost-effective FPGA for whatever sampling speed may be required. Other applications may require 250MHz sampling, or 1GHz, or 1.5GHz. Note that this is an embedded application, so stringing together some dev boards can be effective to prove out chip performance, but ultimately this will be a custom design.Īlso note that the final sampling speed for future work may differ, so I am interested in understanding and comparing key I/O parameters between FPGAs in general. What are the key datasheet parameters I should be paying attention to when looking for an appropriate part? What dictates the limit on an FPGA's I/O communication speed? I'm trying to understand the minimum requirements to interface with an ADC of this caliber. Two ADC chips I am considering are the AD9434 and the ADS5403. How can I tell if one of the cheap FPGAs (example: Spartan-6) I'm looking at is fast enough to keep up with my ADC? For the purposes of the this question, assume the ADC has an LVDS connection. I need relatively fast I/O, and I need it to be cheap. So I don't think I care about how many LUTs, cells, or RAM bits the FPGA has. Basically, I need the 500 MHz sampling speed to capture the physical event, but the FPGA will be selectively discarding most of the samples. The math involved in the FPGA will be minimal. I believe this is a good application for a low-grade FPGA, so I am trying to understand how best to approach selecting a specific FPGA device. I need to take this ADC data and boil it down into something a cheap CPU can process. As another alternative, you should be able to use the FDK-AAC encoder instead of the Core Audio one.īeta Was this translation helpful? Give feedback.I have a project involving an ADC sampling at 500 MHz. For bit rates above 64 kbps total (so 32 kbps per channel for Stereo), the Low Complexity profile is recommended for best quality anyway. Alternatively, you could use the Low Complexity profile instead of the High Efficiency one. Using the Sample Rate Converter in fre:ac to change to a different sample rate before feeding the samples to the encoder should be a viable work-around. When using a newer version of the Core Audio Codec, the issue goes away, but unfortunately that's no option on XP, as there is no newer version for it. The memory leak causes the codec to use more and more memory during encoding and at some point it will exceed either the amount of available RAM or the 32 bit limit of 2 GB per process and crash the application. This appears to be caused by a memory leak in the High Efficiency profile encoder on Apple's side, so unfortunately there is nothing I can do about it. I can reproduce the issue here using the Core Audio Codec files from iTunes 12.1. Hi Alan, you already reported this in an email.
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